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Achieving Significant Capacity Improvements on IBM z13: User Experience

  • Room: L508
  • Session Number: 19488
Wednesday, August 03, 2016: 11:15 AM - 12:15 PM


Todd J. Havekost
Lead Systems Engineer


One of the dominant themes of the z13 processor announcements is that delivered capacity is becoming increasingly dependent on effective utilization of processor cache. Benefit from the experiences of a user who initially experienced a capacity shortfall migrating from zEC12 to z13 models but ultimately achieved significant capacity improvements [and software expense reductions] through a series of configuration changes. In this session, the speaker will review metrics associated with these changes including increasing the number of hardware CPs, LPAR topology, and maximizing the number of Vertical High CPs in the HiperDispatch configuration, as well as interpreting some of the key processor hardware metrics as captured in SMF type 113 records.  This will be an updated version of the session that was selected for a “SHARE Best Session” award at SHARE San Antonio earlier this year. (PCP4) (UX8)

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